This invention relates to a method and apparatus for receiving parallel digital data signals and an aligned frame pulse using a reference clock signal and in particular to aligning the data signals with a locally generated frame pulse which is phase aligned with the reference clock signal.
The requirements of moving vast amounts of information within digital communications systems has led to increases in both the rate at which data is transmitted along a line and the number of lines used in parallel to form data bus structures. Two problems arise when the data signal rate is greater than 10 MHz. The first is devising a technique to sample the data when the data is being clocked at a rate much greater than an order of magnitude above the fastest rate technologically available. The second is providing for a phase shift between the data signal and the reference clock signal of greater than one clock period.
Clock recovery circuits are designed to align the clock signal with the data signal to ensure accurate sampling of the data. One way to provide clocks needed to sample the high rate data signal for aligning the clock signal and the high rate data signal is to provide multiple delayed clock signals by passing the reference clock signal through a multiple tap delay line.
Such a scheme is taught by H. Wong et al. U.S. Pat. No. 4,584,695 issued Apr. 22, 1986 and assigned to National Semiconductor Corporation. In a digital PLL clock recovery scheme Wong et al. disclose a multi-phase clock generator providing clock signals which are phase offset from one another. A single one of these clock signals is then used to sample the data signal, at, slightly before, and after a clock signal transition. The resulting bit pattern is used to determine whether a leading or lagging phase clock should be substituted. The Wong et al. arrangement is applied to Manchester data, that is serial data having an encoded clock signal and a mid-bit transition.
Another scheme is taught by Bergmann et al. U.S. Pat. No. 4,821,297, issued Apr. 11, 1989 and assigned to American Telephone and Telegraph Company. Bergmann et al. use delay lines on both the data and the clock inputs. The delay line on the data input provides phase-shifted data signals to be sampled by a single one of the multiple phase clock signals. As with Wong et al., the resulting bit pattern is used to determine whether a leading or lagging clock signal should be selected. In an alternative embodiment Bergmann et al. use three clock signals of adjacent phase to sample the data signal in place of the data delay line. The Bergmann et al. scheme is applicable to serial data signals and is not dependent upon the coding scheme used for that data.
Silicon CMOS integrated circuits introduce wide time differences or deltas between their best case propagation delays and their worst case propagation delays. The deltas are primarily due to operating temperature variation, supply voltage variation and chip processing variation. As data transmission rates have increased, the magnitude of the deltas can exceed one bit. To transmit the greatest amount of data within the limitations of the technology used, parallel data transmission is chosen, but a scheme for reliable reception of the data is required.